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FPD200
GENERAL PURPOSE PHEMT DIE
FEATURES:
* * * * * 19 dBm Output Power (P1dB) 13 dB Power Gain at 12 GHz 17 dB Maximum Stable Gain at 12 GHz 12 dB Maximum Stable Gain at 18 GHz 45% Power-Added Efficiency
Datasheet v3.0
LAYOUT:
GENERAL DESCRIPTION:
The FPD200 is an AlGaAs/InGaAs pseudomorphic High Electron Mobility Transistor (pHEMT), featuring a 0.25 m by 200 m Schottky barrier gate, defined by highresolution stepper-based photolithography. The recessed gate structure minimizes parasitics to optimize performance. The epitaxial structure and processing have been optimized for reliable medium-power applications.
TYPICAL APPLICATIONS:
* * * * Narrowband and broadband highperformance amplifiers SATCOM uplink transmitters PCS/Cellular low-voltage high-efficiency output amplifiers Medium-haul digital radio transmitters
ELECTRICAL SPECIFICATIONS1:
PARAMETER
Power at 1dB Gain Compression Power Gain at P1dB Noise Figure Power-Added Efficiency Maximum Stable Gain (S21/S12) f = 12 GHz f = 24 GHz
SYMBOL
P1dB G1dB N.F.min PAE MSG
CONDITIONS
VDS = 5 V; IDS = 50% IDSS VDS = 5 V; IDS = 50% IDSS VDS = 5 V; IDS = 50% IDSS VDS = 5V; IDS = 50% IDSS; POUT = P1dB
MIN
18 11.0
TYP
19 13.0 1.2 45
MAX
UNITS
dBm dB dB %
VDS = 5 V; IDS = 50% IDSS
16 10.5
17 12
dB dB
Saturated Drain-Source Current Maximum Drain-Source Current
IDSS IMAX
VDS = 1.3 V; VGS = 0 V VDS = 1.3 V; VGS +1 V VDS = 1.3 V; VGS = 0 V VGS = -5 V VDS = 1.3 V; IDS = 0.2 mA IGS = 0.2 mA IGD = 0.2 mA VDS > 3V
45
60 120
75
mA mA
Transconductance Gate-Source Leakage Current Pinch-Off Voltage Gate-Source Breakdown Voltage Gate-Drain Breakdown Voltage Thermal Resistivity
GM IGSO |VP| |VBDGS| |VBDGD|
80 1 0.7 12.0 14.5 1.0 14.0 16.0 280 10 1.3
mS A V V V C/W
JC
Note: 1 TAmbient = 22C; RF specifications measured at f = 12 GHz using CW signal on a sample basis
1
Specifications subject to change without notice Filtronic Compound Semiconductors Ltd Fax: +44 (0) 1325 306177 Email: sales@filcs.com
Tel: +44 (0) 1325 301111
Website: www.filtronic.com
FPD200
Datasheet v3.0
ABSOLUTE MAXIMUM RATING :
PARAMETER
Drain-Source Voltage Gate-Source Voltage Drain-Source Current Gate Current RF Input Power Channel Operating Temperature Storage Temperature Total Power Dissipation Gain Compression 4 Simultaneous Combination of Limits 2 or more Max. Limits 80%
1
SYMBOL
VDS VGS IDS IG PIN TCH TSTG PTOT Comp.
TEST CONDITIONS
6 -3V < VGS < -0.5V 0V < VDS < +8V For VDS < 2V Forward or reverse current Under any acceptable bias state Under any acceptable bias state Non-Operating Storage See De-Rating Note below Under any bias conditions
ABSOLUTE MAXIMUM
8V -3V IDSS 10mA 20dBm 175C -65C to 150C 0.5W 5dB
Notes: 1 TAmbient = 22C unless otherwise noted; exceeding any one of these absolute maximum ratings may cause permanent damage to the device 2 Total Power Dissipation defined as: PTOT (PDC + PIN) - POUT, where PDC: DC Bias Power, PIN: RF Input Power, POUT: RF Output Power 3 Total Power Dissipation to be de-rated as follows above 22C: PTOT= 500mW - (3.6mW/C) x THS where THS= heatsink or ambient temperature above 22C Example: For a 85C carrier temperature: PTOT = 500 - (3.6mW x (85 - 22)) = 0.27W 4 Users should avoid exceeding 80% of 2 or more Limits simultaneously 5 Thermal Resitivity specification assumes a Au/Sn eutectic die attach onto a Au-plated copper heatsink or rib. 6 Operating at absolute maximum VD continuously is not recommended. If operation at 8V is considered then IDS must be reduced in order to keep the part within it's thermal power dissipation limits. Therefore VGS is restricted to < -0.5V.
PAD LAYOUT:
PAD
DESCRIPTION
C1 A C2 B
A B C1/C2 Gate Pad Drain Pad Source Pad
PIN COORDINATES (m)
90, 200 320, 200 200, 290/110
Note: Co-ordinates are referenced from the bottom left hand corner of the die to the centre of bond pad opening
DIE SIZE (m)
400 x 400
DIE THICKNESS (m)
75
MIN. BOND PAD OPENING (m x m )
70 x 80
2
Specifications subject to change without notice Filtronic Compound Semiconductors Ltd Fax: +44 (0) 1325 306177 Email: sales@filcs.com
Tel: +44 (0) 1325 301111
Website: www.filtronic.com
FPD200
Datasheet v3.0
TYPICAL MEASURED PERFORMANCE :
FPD200 Biased @ 5V, 27mA
35 30
FPD200 Biased @ 8V, 27mA
MSG S21
MSG (dB)
35 30 25 20 15 10 5 0
MSG S21
MSG (dB) &
25 20 15 10 5 0 0.5 2.5 4.5 6.5 8.5 10.5 12.5 14.5 16.5 18.5 20.5 22.5 24.5 26 Frequency (GHz)
Mag S21
Mag S21
&
0.5
2.5
4.5
6.5
8.5 10.5 12.5 14.5 16.5 18.5 20.5 22.5 24.5 26 Frequency (GHz)
Associated Gain and N.F.min vs Frequency Biased @ 3V, 27mA
22.0 20.0 18.0 16.0 14.0 12.0 10.0 8.0
Associated Gain and N.F.min vs Frequency Biased @ 5V, 27mA
3.5 3 2.5 2 1.5 1 0.5 0
22.0 20.0
Gain (dB) N.F.min
Gain (dB) N.F.min
3.5 3
Associated Gain (dB)
Associated Gain (dB)
N.F.min (dB)
16.0 14.0 12.0 10.0 8.0 10.0 11.0 12.0 13.0 14.0 15.0 16.0 17.0 18.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0
2 1.5 1 0.5 0
10.0
11.0
12.0
13.0
14.0
15.0
16.0
17.0
Frequency (GHz)
18.0
2.0
3.0
4.0
5.0
6.0
7.0
8.0
9.0
Frequency (GHz)
TYPICAL WAFER DISTRIBUTIONS:
Note: Data taken from a typical wafer at ambient temperature. Future wafers may have nominal values anywhere within the specifications range.
LSL = 0.045 A 5000 4000
Mean StDev N 0.06103 0.003473 23955
USL = 0.075 A
LSL= -1.3 V 3000 2500 2000
Mean StDev N -0.8820 0.02686 23867
USL = -0.7 V
Frequency
3000 2000 1000
Frequency
1500 1000 500
0 0.040
0.045
0.050
0.055
0.060 0.065 IDSS (A)
0.070
0.075
0.080
0
-1.3
-1.2
-1.1
-1.0 VP (V)
-0.9
-0.8
-0.7
3
Specifications subject to change without notice Filtronic Compound Semiconductors Ltd Fax: +44 (0) 1325 306177 Email: sales@filcs.com
Tel: +44 (0) 1325 301111
Website: www.filtronic.com
N.F.min (dB)
18.0
2.5
FPD200
Datasheet v3.0
NOISE PARAMETERS :
(Biased @ VDS=3V, IDS=27mA)
HANDLING PRECAUTIONS:
Gamma Opt. Angle 6.70 14.60 22.60 27.90 34.90 41.50 47.50 54.40 60.20 65.70 78.60 89.70 95.90 103.70 113.50 137.10 156.80 0.75 0.71 0.74 0.62 0.63 0.54 0.48 0.43 0.41 0.41 0.34 0.28 0.24 0.23 0.24 0.17 0.20
To avoid damage to the devices care should be exercised during handling. Proper Electrostatic Discharge (ESD) precautions should be observed at all stages of storage, handling, assembly, and testing. These devices should be treated as Class 0 (0-250 V) as defined in JEDEC Standard No. 22-A114. Further information on ESD control measures can be found in MIL-STD-1686 and MIL-HDBK-263.
Freq (GHz) 2.00 3.00 4.00 5.00 6.00 7.00 8.00 9.00 10.00 11.00 12.00 13.00 14.00 15.00 16.00 17.00 18.00
N.F.min (dB) 0.32 0.41 0.52 0.55 0.62 0.78 0.87 1.00 1.08 1.20 1.28 1.37 1.55 1.70 1.85 1.99 2.09
Rn/50 0.31 0.31 0.29 0.28 0.26 0.26 0.26 0.25 0.24 0.24 0.24 0.24 0.22 0.20 0.20 0.19 0.18
(Ohms) Mag
APPLICATION NOTES & DESIGN DATA:
Application Notes and design data including Sparameters, noise parameters and device model are available on request
DISCLAIMERS:
This product is not designed for use in any space based or life sustaining/supporting equipment.
ORDERING INFORMATION: PREFERRED ASSEMBLY INSTRUCTIONS:
GaAs devices are fragile and should be handled with great care. Specially designed collets should be used where possible. The recommended die attach is gold/tin eutectic solder under a nitrogen atmosphere. Stage temperature should be 280-290C; maximum time at temperature is one minute. The recommended wire bond method is thermo-compression wedge bonding with 0.7 or 1.0 mil (0.018 or 0.025 mm) gold wire. Stage temperature should be 250-260C. PART NUMBER
FPD200
DESCRIPTION
Die
4
Specifications subject to change without notice Filtronic Compound Semiconductors Ltd Fax: +44 (0) 1325 306177 Email: sales@filcs.com
Tel: +44 (0) 1325 301111
Website: www.filtronic.com

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